1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory device in which a plurality of semiconductor chips that include a memory cell array chip are stacked.
2. Description of the Related Art
The miniaturization of semiconductor integrated circuits has raised the degree of integration and has thus advanced the development of higher capacities in DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). However, because there are limits to the miniaturization of semiconductors, new technologies are being sought to achieve further increases in the degree of integration.
Three-dimensional semiconductors, in which semiconductor chips are stacked, have been proposed as one technology for raising the degree of integration of memory. Japanese Patent Laid-Open Publication No. H04-196263 describes a means for realizing a large-scale integrated circuit without changing the chip area by stacking semiconductor chips and discloses the integration of memory circuits on a separate chip that is stacked on the main body of a semiconductor integrated circuit. In addition, Japanese Patent Laid-Open Publication No. 2002-026283 describes a multilayer memory configuration in which memory cell arrays are multilayered to obtain greater capacity.
Multilayering of semiconductor chips necessitates interconnections between semiconductor chips in addition to the previously required interconnections within the semiconductor chip area. As the interconnections between semiconductor chips, vias that pass through semiconductor chips have been proposed as a means of increasing interconnection density. In K. Takahashi et al. in the Japanese Journal of Applied Physics, 40, 3032 (2001), a technology is disclosed in which a silicon chip was thinned to 50 μm, square holes measuring 10 μm on each side were opened in the silicon chip, and these holes were then filled with a metal to form vias for use in interconnections between semiconductor chips. The interconnections between semiconductor chips that are realized by these vias can be arranged two-dimensionally within the surface of a semiconductor chip, and thus allow several hundred interchip interconnections.
In-plane interconnections can be long because the dimension of one edge of a semiconductor chip may be greater than 10 mm, while the length of semiconductor interchip interconnections can be extremely short because the thickness of a semiconductor chip is on the order of just 50 μm. Accordingly, when transferring data between a plurality of stacked semiconductor chips, the use of a multiplicity of interconnections between semiconductor chips that are arranged two-dimensionally within the area of the semiconductor chips, as with vias, allows a reduction of the total interconnection length of the three-dimensional interconnections.
FIG. 1 is a plan view showing the interconnections of a memory cell array in which a plurality of memory cell arrays are arranged in a plane without using interconnections between chips, and FIG. 2 is a plan view showing a memory cell array chip having a number n of banks 20.
As shown in FIG. 1, a memory cell array chip of the prior art is provided with a plurality of memory cell arrays 10 that are configured as banks for the purpose of interleaving memory access operations. Each memory cell array 10 is provided with row decoder 12 and column decoder 13 for carrying out read and write operations. In addition, each memory cell array 10 has DQ11 (which are data lines for input/output of one bit, these being paired lines in some cases) for all input/output bits (DQ0, DQ1, DQ2, and DQ3), and when one interchip interconnection is used for each bit for transferring data between chips, a plurality of interconnections of a length on the order of the chip size is necessary within the chip area for collecting the DQ lines for each bit from all banks that are arranged over the entire chip area.
As shown in FIG. 2, each bank has memory regions for all input/output bits, and in-plane interconnections are therefore required for DQ lines that connect the banks that are distributed over the entire area of the chip surface.
This in-plane interconnection is further necessary for the number of stacked memory cell array chips. In contrast, when interchip interconnections are provided for input/output bits in each and every memory cell array 10, the need for long interconnections between in-plane banks can be eliminated, and increase in the three-dimensional interconnection length can therefore be suppressed despite increase in the number of stacked chips.
As explained in the foregoing explanation, the application of interchip interconnections to a semiconductor memory device, in which semiconductor chips are stacked, is effective for suppressing an increase in the interconnection length. Nevertheless, vias that are used in three-dimensional interchip interconnections have a problem of greater capacitance than ordinary in-plane interconnections. Compared to in-plane chip interconnections, which have a thickness of just 1 μm or less, vias must have a thickness of 10 μm or more due to processing restrictions, and further, these vias are enclosed by the silicon substrate chip and further have a long perimeter, whereby vias exhibit considerable parasitic capacitance with the substrate.
As an example, when a via having a circular cross section with a diameter of 20 μm passes through a silicon substrate that is interposed between dielectric films having a thickness of 250 nm, the thickness of the substrate will be 50 μm, i.e., the length of the via will be 50 μm, and the capacitance will reach 0.45 pF. In-plane interconnections that are normally used have a capacitance on the order of 0.2 pF per 1 mm, and this via capacitance is therefore equivalent to approximately 2 mm of in-plane interconnections. Thus, when a multiplicity of interchip interconnections are used to transfer data between chips, the interconnection capacitance will not be small despite the reduction in the total interconnection length. In particular, in the case of a memory cell array chip with a configuration in which one chip has a plurality of banks, interchip interconnections must be provided for the number of banks for each one-bit DQ line. This increase in interconnection capacitance raises the problem of increased power consumption of the memory device.